Digital delta mode carrier sense for a wireless LAN

ABSTRACT

An apparatus and a method for detecting a carrier signal of a phase shift keyed modulated signal. A first counter circuit generates a plurality of counts, with each count being a number of cycles of a reference frequency signal occurring between two consecutive rising edges of an intermediate frequency signal. A comparison circuit compares a first count of reference frequency cycles to a second count of reference frequency cycles when a difference between an initial count of reference frequency cycles and a first predetermined number is less than a second predetermined number. The first predetermined number represents a time period of one cycle of the nominal center frequency, and the first count and the second count respectively represent time periods of first and second cycles of a pair of consecutive cycles of the intermediate frequency signal. The comparison circuit generates a difference signal when a difference between the first count and the second count is less than a third predetermined number. A second counter circuit counts cycles of the intermediate frequency signal and generates a carrier detect signal when a count of the intermediate frequency signal cycles equals a fourth predetermined number.

FIELD OF THE INVENTION

The present invention broadly relates to data processing systems. Moreparticularly, the present invention relates to digital input/outputsystems for communication over a radio medium.

BACKGROUND OF THE INVENTION

Phase shift key (PSK) modulation of radio signals has been used in thepast to transmit digital information between data processing systems.One example is shown in U.S. Pat. No. 5,150,070, entitled "Demodulatorfor biphase, suppressed-carrier PSK signals" by P. Rinaldi. The phasemodulation technique uses a 180 degree phase shift to distinguishbetween a binary one and a binary zero. This forces the carrier to bezeroed-out during modulation. To demodulate the modulated signal, theprior art requires complex circuitry to reliably reconstitute the binaryinformation at the receiver. The demodulators of the prior art mustreconstruct the carrier. They require coherent demodulation to create asignal that is phase locked with the incoming signal, and they then mustcombine the two in a multiplier to detect the data. Consequently, the IFsignal must be made synchronous with the demodulated signal off thecarrier. Stated otherwise, the carrier and the local oscillator must bemade synchronous to demodulate the PSK signal.

In phase shift key modulation, a carrier signal, for example a 2.4 GHzcarrier signal, is selectively applied to a phase shift delay circuit,depending upon the binary state of control input to the delay circuit.For example, when there is a binary zero data state for the controlinput, no phase shift delay is applied to the carrier signal.Alternately, when there is a binary one data state, a phase shift delayis applied to the carrier signal. The carrier signal is then transmittedto the receiver. At the receiver, there is a local oscillator thatoscillates at a slightly different frequency, for example 2.4 GHz plus 2MHz. At the receiver, these two frequencies are mixed and acorresponding beat note signal, or intermediate frequency (IF) signal,is produced. Phase shift information, which has been imposed on thecarrier signal, is then manifested in the IF signal at the receiver. Asignificant problem in such phase shift key modulation communicationtechniques is created by the drift in the frequency of the oscillator atthe transmitter which generates the 2.4 GHz carrier signal, and thedrift of the local oscillator at the receiver which generates the 2.4GHz plus 2 MHz signal. The relative drift in the frequencies of thesetwo oscillators results in unstable characteristics in the intermediatefrequency produced at the receiver and, therefore, unreliable detectionof the binary data being transmitted.

U.S. Pat. No. 5,561,689, filed Oct. 26, 1994, by Fleek et al., disclosesa phase demodulation technique for wireless LAN that allows the carrierand the local oscillator to not be synchronous. A PSK modulated signalreceived at a receiving station is amplified by a limit amplifier toform a square wave signal having pulses of uniform height. To detect acarrier sense condition, the time between the rising edges of the squarewave IF signal that occur in response to the modulation at thetransmitter are detected using a counter during a carrier sensemeasurement window. Times between the like edges of the square wavesignal that are shorter than normal for an unmodulated IF signalindicate a first binary value of the modulation. Longer than normaltimes between the like edges of the square wave IF signal indicate asecond binary value.

To compensate for drift in the carrier and in the local oscillatorfrequencies, the nominal non-phase transition portions of the IF signalare periodically sampled and corresponding registers are updated.Nevertheless, for a reliable carrier sense indication the IF frequencyof the receiving station is required to be constant for a large numberof cycles. This requirement greatly constrains the difference in crystalreferences between the transmitting and receiving stations and makes themeasurement window for detecting a carrier sense indication relativelylarge. Other factors associated with this particular approach thatcontribute to the requirement of a large measurement window are, forexample, the phase noise of the voltage controlled oscillator (VCO) ofthe local oscillator (LO), and variations in the LO frequency that arecaused by the phase locked loop (PLL) not being completely settled. Bymaking carrier sense measurement window sufficiently large to allow forthese factors, this particular technique occasionally provides falsecarrier sense indications, adversely affecting the reliability of thecollision avoidance algorithm provided by the Media Access Control layerof the wireless LAN system. For example, after a crier sense conditionis active, the measurement window is expanded to allow for thevariations in the IF that are caused by the Phase Shift Modulation. As aresult, a carrier sense indication occasionally remains active aftertransmission of a data frame is complete.

What is needed is a demodulation technique that permits the crystalreferences at both the transmitting and receiving stations of a wirelessnetwork to have a greater frequency tolerance, %hat prevents slowchanges in the LO caused by PLL settling time to adversely affectcarrier sense indications, and that reliably senses the end of a dataframe and loss of the carrier.

OBJECTS OF THE INVENTION

It is an object of the invention to provide a wireless local areanetwork that has a more reliable and accurate reception of digitaltransmissions from a sending node, than has been available in the priorart.

It is another object of the invention to provide a wireless local areanetwork that has a better carrier signal detection than has beenavailable in the prior art.

It is another object of the invention to provide a wireless local areanetwork in which a carrier sense condition is detected based on aminimum change from cycle to cycle of the carrier signal.

It is another object of the invention to permit the crystal referencesat both the transmitting and receiving stations of a wireless network tohave a greater frequency tolerance.

It is another object of the invention to prevent slow changes in the LOcaused by PLL settling time to adversely affect carrier senseindications.

It is another object of the invention to reliably sense the end of adata frame and loss of the carrier.

SUMMARY OF THE INVENTION

These and other objects, features and advantages are accomplished by thepresent invention. In that regard, the present invention provides anapparatus for detecting a carrier signal of a phase shift keyedmodulated signal representing a binary signal. The apparatus istypically part of a receiving node that is associated with a sendingnode in a wireless local area network. According to the invention, theapparatus includes an intermediate frequency generator, an edgedetecting circuit, a first counter circuit, a comparison circuit, asecond counter circuit and a media access control device. Theintermediate frequency generator receives a phase shift keyed modulatedsignal and generates an intermediate frequency signal having rising andfalling edges and a nominal center frequency. The edge detecting circuitis coupled to the intermediate frequency signal and detects consecutiverising and falling edges of the intermediate frequency signal, where twoconsecutive rising edges represent a time period of a cycle of theintermediate frequency signal. Similarly, two consecutive falling edgesrepresent a time period of a cycle of the intermediate frequency signal.The first counter circuit is responsive to the edge detecting circuit bygenerating a plurality of counts, such that each count is the number ofcycles of a reference frequency signal that occur between twoconsecutive rising edges. The comparison circuit is responsive to thefirst counter circuit by comparing a first count of reference frequencycycles to a second count of reference frequency cycles when a differencebetween an initial count of reference frequency cycles and a firstpredetermined number is less than a second predetermined number.According to the invention, the first predetermined number represents atime period of one cycle of the nominal center frequency, and the secondpredetermined number preferably corresponds to about 50 ns. The firstand second counts respectively represent time periods of first andsecond cycles of a pair of consecutive cycles of the intermediatefrequency signal. Of the first and second counts, at least the secondcount occurs subsequent to the initial count. That is, the first countand the initial count may be identical. Preferably, the comparisoncircuit compares the first count to the second count when the initialcount falls within a predetermined range of numbers, with thepredetermined range of numbers corresponding to a range of time periodsrelated to one time period of the nominal center frequency. Thecomparison circuit then generates a difference signal when a differencebetween the first count and the second count is less than a thirdpredetermined number that preferably corresponds to about 36 ns. Thesecond counter circuit is responsive to the difference signal bycounting cycles of the intermediate frequency signal and generates acarrier detect signal when a count of the intermediate frequency signalcycles equals a fourth predetermined number that preferably correspondsto about 74 cycles. The media access control device is responsive to thecarrier detect signal by disabling the sending node associated with thereceiving node from transmitting a signal.

According to the invention, the edge detecting circuit includes a limitamplifier that generates a square wave pulse signal having rising andfalling edges and that corresponds to the intermediate frequency signal.The edge detecting circuit detects consecutive rising edges andconsecutive falling edges of the square wave pulse signal. Thecomparison circuit includes a storage circuit, a decoder circuit and anadder circuit. The storage circuit is coupled to the first countercircuit and stores the first and second counts representing therespective time periods of the first and second cycles of a pair ofconsecutive cycles of the intermediate frequency signal. The decodercircuit is coupled to the storage circuit and outputs a first signalwhen the initial count of cycles is less than the second predeterminednumber. The second counter circuit is responsive to the first signal byresetting the count of cycles of the intermediate frequency signal. Theadder circuit is coupled to the storage circuit and outputs thedifference signal when the difference between the first and secondcounts is less than the third predetermined difference.

The invention also includes a third counter circuit, a data outputcircuit and a frequency compensation circuit. The third counter circuitis responsive to the edge detecting circuit by generating a plurality ofcounts, such that each count counted by the third counter circuit is anumber of cycles of the reference frequency signal occurring between twoconsecutive falling edges. The data output circuit is responsive to therespective counts of the first and third counter circuits by generatingan output signal that is a composite representation of the binarysignal. The frequency compensation circuit outputs a frequencycompensation signal when the second counter circuit generates thecarrier detect signal. Preferably, the frequency compensation signal isrelated to a difference between a time period of a cycle of theintermediate frequency signal and a time period of one cycle of thenominal center frequency. The first and third counter circuits arecoupled to the frequency compensation signal, and the first and thirdcounter circuits each output a plurality of counts that are offset bythe frequency compensation signal.

After the carrier detect signal is generated, the comparison circuitcompares a third count of cycles of the reference frequency counted bythe first counter circuit to the first predetermined number. Thecomparison circuit then terminates the difference signal when adifference between the third count and the first predetermined numberequals a fifth predetermined number that preferably corresponds to about55 ns. The second counter circuit is responsive to termination of thedifference signal by counting cycles of the intermediate frequencysignal and terminating the carrier detect signal when a count of theintermediate frequency signal cycles equals a sixth predetermined numberthat preferably corresponds to about 5 cycles of the intermediatefrequency signal. The media access control device is responsive totermination of the carrier detect signal by enabling the associatedsending node for transmitting a signal.

The present invention also provides a wireless local area network thatincludes a first node having a transmitting device that transmits aphase shift keyed modulated signal that represents a binary signal, anda second node having a transmitting device and a receiving device thatreceives the signal transmitted by the first node. The receiving deviceof the second node includes an intermediate frequency generator, acarrier detection circuit, a cycle-to-cycle difference circuit, a cycledifference counter circuit, a media access control device, a demodulatorcircuit and a frequency compensation circuit. The intermediate frequencygenerator generates an intermediate frequency signal corresponding tothe received signal. The carrier detection circuit is coupled to theintermediate frequency generator and measures a time period of a cycleof the intermediate frequency signal. The carrier detection circuitgenerates a first detection signal when a difference between themeasured time period and a nominal time period of the intermediatefrequency signal is less than a first predetermined difference thatpreferably corresponds to about 50 ns. The cycle-to-cycle differencecircuit measures a difference in time periods of two consecutive cyclesof the intermediate frequency signal and generates a valid differencesignal when the difference is less than a second predetermineddifference that preferably corresponds to about 36 ns. The cycledifference counter circuit is responsive to the first detection signaland the valid difference signal by counting cycles of the intermediatefrequency signal and by generating a carrier detect signal when a countof the intermediate frequency signal cycles equals a first predeterminednumber that preferably corresponds to about 74 cycles of theintermediate frequency signal.

The media access control device disables the transmitting device of thesecond node from transmitting a signal when the carrier detect signal isgenerated. The demodulator circuit generates a composite output signalcorresponding to the binary signal when the carrier detect signal isgenerated. The frequency compensation circuit is responsive to thecarrier detect signal by generating a frequency compensation signal thatis preferably related to a difference between a time period of a cycleof the intermediate frequency signal and a time period of one cycle ofthe nominal center frequency.

According to the invention, the carrier detection circuit includes amemory circuit that stores measured time periods of two consecutivecycles of the intermediate frequency signal, and a decoder circuit thatgenerates the first detection signal when the difference between one ofthe stored measured time periods and the nominal time period of theintermediate frequency signal is less than the first predetermineddifference. The memory circuit is coupled to the frequency compensationsignal and the measured time periods of the two consecutive cycles ofthe intermediate frequency signal are compensated by the frequencycompensation signal. The cycle-to-cycle difference circuit includes anadder circuit that is coupled to the memory circuit and outputs thevalid difference signal when the difference between the two storedmeasured time periods is less than the second predetermined difference.The decoder circuit terminates the first detection signal when thedifference between the one of the stored measured time periods and thenominal time period of the intermediate frequency signal equals thefirst predetermined difference. The cycle difference counter circuit isresponsive to termination of the first detection signal by resetting thecount of the cycles of the intermediate frequency signal.

After the carrier detect signal is generated, the cycle-to-cycledifference circuit measures a difference between a time period of acycle of the intermediate frequency signal and the nominal time periodof the intermediate frequency signal, and generates a valid differencesignal when the difference is less than a third predetermined differenceand terminates the valid difference signal when the difference equalsthe third predetermined difference. The cycle-to-cycle differencecircuit is responsive to termination of the valid difference signal bycounting cycles of the intermediate frequency signal and by terminatingthe carrier detect signal when a count of the intermediate frequencysignal cycles equals a second predetermined number. Preferably, thethird predetermined difference corresponds to about 55 ns, and thesecond predetermined number corresponds to about 5 cycles of theintermediate frequency signal. The media access control device isresponsive to termination of the carrier detect signal by enabling thetransmitting device of the second node for transmitting a signal.

The present invention also provides a method of detecting a carriersignal of a phase shift keyed modulated signal. The method includes thesteps of generating an intermediate frequency signal from a receivedphase shift keyed modulated signal, with the intermediate frequencysignal having a nominal center frequency; determining a differencebetween a time period of a first cycle of the intermediate frequencysignal and a time period of one cycle of the nominal center frequency;determining a first difference between cycle time periods of each cyclefor each pair of consecutive cycles of the intermediate frequency signalfor a first predetermined number of consecutive cycles of theintermediate frequency signal when the determined difference between thetime period of the first cycle of the intermediate frequency signal andthe time period of one cycle of the nominal center frequency is lessthan a predetermined period of time, with the consecutive cycles beingsubsequent to the first cycle; and generating a carrier detect signalwhen the first difference between cycle time periods of each cycle foreach pair of the first predetermined number of consecutive cycles of theintermediate frequency is less than a first predetermined cycle timeperiod difference. Preferably, the first predetermined number ofconsecutive cycles is about 74 consecutive cycles, the predeterminedperiod of time is about 50 ns, and the first predetermined cycle timeperiod difference is about 36 ns. Transmission of a signal is disabledwhen the carrier detect signal is generated.

According to the invention, the step of generating an intermediatefrequency signal includes the step of forming a square wave pulse signalfrom the received signal, that represents a binary signal, such that thesquare wave pulse signal has rising and falling edges. Additionally, thestep of determining the difference between the time period of the firstcycle of the intermediate frequency signal and the time period of onecycle of the nominal center frequency includes the steps of detectingfirst and second consecutive rising edges of the square wave pulsesignal, with the first and second consecutive rising edges representingthe first cycle of the intermediate frequency signal; measuring a firstnumber of periods of a first predetermined frequency signal occurringbetween the first and second rising edges, with the first numberrepresenting the time period of the first cycle; and comparing the fistnumber with a predetermined number that preferably represents the timeperiod of one cycle of the nominal center frequency.

The step of determining the first difference between cycle time periodsof each cycle for each pair of consecutive cycles of the intermediatefrequency signal includes the steps of detecting third and fourthconsecutive rising edges of the square wave pulse signal, with the thirdand fourth consecutive rising edges representing a first cycle of a pairof consecutive cycles of the intermediate frequency signal; measuring asecond number of periods of the first predetermined frequency signaloccurring between the third and fourth rising edges, with the secondnumber representing the time period of the first cycle of the pair ofconsecutive cycles; detecting a fifth rising edge of the square wavepulse signal, the fifth rising edge being consecutive to the fourthrising edge, such that the fourth and fifth consecutive rising edgesrepresents a second cycle of the pair of consecutive cycles; measuring athird number of periods of the first predetermined frequency signaloccurring between the third and fourth rising edges, with the thirdnumber representing the time period of the second cycle of the pair ofconsecutive cycles; and determining a difference between the secondnumber and the third number. Preferably, the first and second risingedges are the third and fourth rising edges, respectively, such that thefirst cycle of the intermediate frequency signal is the first cycle ofthe pair of consecutive cycles.

The received signal is demodulated to generate an output signal that isa composite representation of the binary signal when the carrier detectsignal is generated. The received signal is demodulated by measuringfirst time intervals between consecutive rising edges of the square wavepulse signal; measuring second time intervals between consecutivefalling edges of the square wave pulse signal; and generating the outputsignal based on results of the first and second time intervalmeasurements. The method of the invention also includes the steps ofmeasuring a cycle time period of a second cycle of the intermediatefrequency signal when the cycle time period difference for each pair ofthe first predetermined number of consecutive cycles is less than thefirst predetermined cycle time period difference, such that the secondcycle is subsequent to the first predetermined number of consecutivecycles; generating a frequency compensation factor based on the measuredsecond cycle time period; and compensating the first and second timeintervals measurements for cycle time period deviations of theintermediate frequency signal from the cycle time period of the nominalcenter frequency using the frequency compensation factor.

The method of the invention also includes the steps of determining asecond difference between cycle time periods of each cycle for each pairof consecutive cycles of the intermediate frequency signal for a secondpredetermined number of consecutive cycles of the intermediate frequencysignal after the carrier detect signal is generated; and terminating thecarrier detect signal when the second difference between cycle timeperiods of each cycle for each pair of the second predetermined numberof consecutive cycles of the intermediate frequency is less than asecond predetermined cycle time period difference. Preferably, thesecond predetermined number of consecutive cycles is about 5, and thesecond predetermined cycle time period difference is about 55 ns.

DESCRIPTION OF THE FIGURES

These and other objects, features and advantages will be more fullyappreciated with reference to the accompanying figures.

FIG. 1A is a waveform diagram of the intermediate frequency (IF)demodulation.

FIG. 1B is a waveform diagram illustrating the digital filtering in thedemodulator of the invention.

FIG. 2 is a functional block diagram of the local area network,including the sending node and the receiving node, in accordance withthe invention.

FIG. 2A shows an alternate embodiment of the modulator 106, with a fixedphase shift value of 90°.

FIG. 2B shows the preferred embodiment of the modulator 106, which usesan adjustable phase shift value which is set at 122° phase shift.

FIG. 3 is a functional block diagram of the demodulator 122 in thereceiver, in accordance with the invention.

FIG. 4 is a logic block diagram of the carrier sense circuit, inaccordance with the invention.

FIG. 5 is a logic block diagram of the frequency compensation circuit,in accordance with the invention.

FIG. 6 is a logic block diagram of the digital filter and intermediatefrequency edge detector, in accordance with the invention.

FIG. 7 is a logic block diagram of the positive edge data demodulatorcircuit, in accordance with the invention.

FIG. 8 is a logic block diagram of the negative edge data demodulatorcircuit, in accordance with the invention.

FIG. 9 is a logic block diagram of the digital filter and data outputcircuit, in accordance with the invention.

FIG. 10 is a timing diagram of the carrier sense operation.

FIG. 11 is a timing diagram of the data demodulation operation of theinvention.

FIG. 12 is a logic block diagram of the clock pulse generation circuit.

FIG. 13 is a functional block diagram of the local area network, showingthe carrier detection spoiler signal generator 170 at the transmitter.

FIG. 14 is a schematic diagram of the carrier detection spoiler signalgenerator circuit 170.

FIG. 15A is a waveform diagram of the intermediate frequency signal Dwhich is modulated by the spoiler signal SP.

FIG. 15B is a waveform diagram of signal D for the intermediatefrequency after the spoiler signal SP no longer modulates the carriersignal.

FIG. 16 is a functional block diagram of a complete transmitter/receivernode in the local area network of FIG. 2.

FIG. 17 is an illustration of a message which is transmitted over aradio link, and which includes a trailer portion with a specifiedfrequency hopping sequence.

DISCUSSION OF THE PREFERRED EMBODIMENT

The waveform diagram of FIG. 1A illustrates a 0.5 megabit per seconddata rate waveform A showing a binary state 1 (A=1) interval which endsat the time T1 with a transition from a binary 1 to a binary 0 state.The time in nanoseconds is shown along the abscissa of the waveform andit is seen that at 2000 nanoseconds, the T1 event occurs. After time T1and before time T2, the data waveform is in a binary 0 state (A=0). Atthe instant T2, a transition from binary 0 to binary 1 occurs with A=1.

Reference can be made to the system block diagram of FIG. 2 whichillustrates how the transmitter at the local area network sending node110 transmits the information in the data waveform A. A source computer102 outputs binary digital information to the local area networkinterface adapter 104, which outputs a 500 Kbps binary data stream A.The data rate for the binary data stream A can have other values up to1/2 of the IF frequency D in FIG. 1A. Thus, if the IF frequency ishigher, for example at 20 MHz, then the data rate can have any value upto 10 megabits per second, for example. A 2.4 GHz oscillator 100generates the carrier signal B. The carrier signal B is applied to thephase shift key (PSK) modulator 106. The control signal which is thebinary signal A is applied to the modulator 106. Modulation occurs whenthe waveform A transitions from the binary A=1 to binary A=0 at the timeT1; a phase shift delay is applied to the carrier signal B. Alternately,when the data waveform A transitions from a binary value A=0 to a binaryvalue A=1 at time T2, the phase shift delay is removed from the carriersignal B. This modulated carrier signal is then applied as signal C tothe radio transmitter 108 at the local area network sending node 110. Anelectromagnetic radio wave 115 is transmitted from the transmitter 108to the radio receiver 116 at the local area network receiving node 130in FIG. 2. The receiver 116 then outputs the waveform C to the input ofthe signal mixer 120. The local oscillator 118 at the receiving node130, has a frequency of 2.4 GHz+2 MHz. The local oscillator at thereceiving node could also have a frequency of 2.4 GHz-2 MHz, forexample. The local oscillator signal B' is applied to the other input tothe mixer 120, resulting in a heterodyned beat signal C' which is the 2MHz intermediate frequency signal. The 2 MHz intermediate frequencysignal at C' is applied to a low pass filter 150 whose output 121 isthen applied to the PSK demodulator 122. The demodulator 122 is shown ingreater detail in FIG. 3. The output of the demodulator 122 is a binarydata stream A' which is the reconstructed data stream A which wasapplied to the input of the modulator 106 at the sending node 110. Theoutput of the demodulator 122 on line 123 is applied to the local areanetwork interface adapter 124 and then to the destination computer 126at the local area network receiving node 130.

FIG. 2A shows an embodiment for the modulator 106, wherein a 90° phaseshift is applied when the binary signal A transitions from a binaryvalue of one to a binary value of zero. Alternately when the datawaveform A transitions from a binary value of zero to a binary value ofone, the phase shift delay is removed from the carrier signal B.Inspection of the waveform diagram A in FIG. 1A will show that thetransition from the binary one to the binary zero is substantiallyinstantaneous. When a 90° phase shift is applied to the carrier signal Bduring an extremely small interval, undesirable harmonic frequencies aregenerated which make the design difficult to comply with the FederalCommunications Commission Part 15 spectral requirements.

FIG. 2B shows the preferred embodiment for the modulator 106, and thebest mode of the invention, with the phase angle for the phase shifthaving a value of 122°, applied over an interval less than, butapproximately equal to the period of the intermediate frequency of 500nanoseconds. In FIG. 2A, the modulator 106 is designed to apply thephase shift over a duration which is less than and approximately equalto the intermediate frequency period of 500 nanoseconds. In order toincrease the detectability of the phase shift signal at the receiver,the magnitude of the phase shift angle is increased from 90° up to 130°.Phase shift magnitudes from 90° to 130° are found to work well. The bestmode for the phase shift angle is found to be 122°. The modulator 106 ofFIG. 2B accomplishes the phase modulation as follows. The binary signalA is applied to the input of the filter 140, which is a low pass filter.The filter 140 includes a notch filter at 0.75 MHz, to suppressundesirable harmonics. The output of the filter 140, is applied on line144 to the input of the vector modulator 142. The wave form V for theoutput on line 144 from the filter 140, is shown in the waveform 145. Itis seen in the waveform 145 shown in FIG. 2B, that the duration overwhich the binary value of the signal A changes from a binary one tobinary zero, is approximately 500 nanoseconds, which is the intermediatefrequency. This is compared with the waveform 141 shown in FIG. 2B forthe binary waveform A input to filter 140. The vector modulator 142 hasan adjustable input 146 which allows the setting of the maximum valuefor the phase angle to be applied by the vector modulator 142 to thecarrier signal B. Settings for the maximum value phase angle 146 can befixed from 90° to 130° and a satisfactory modulated carrier signal C canbe obtained. In the best mode of the invention, the setting for themaximum value phase angle 146 is found to be a value of 122 degrees.

Returning to FIG. 1A, it can be seen that the intermediate frequencysignal C' output from the mixer 120 in FIG. 2 is an approximately 2 MHzsinewave signal whose phase is modulated by the 500 Kbps digital signalA. The modulation shown for FIGS. 1A and 1B is instantaneous 90° phaseshift when the binary data A transitions from a binary one to a binaryzero. This is done to simplify the illustration of the invention.

In FIG. 3, the demodulator 122 has its input 121 connected to the limitamplifier 200, for amplifying the filtered intermediate frequency signalC' to form the square wave, limit-amplified signal D shown in FIG. 1A.The square wave signal D will have its zero crossings at the sameinstant as the zero crossings of the sinewave signal C'. It can be seenby inspection of FIG. 1A, that the duration of each period for thewaveform D remains approximately 500 nanoseconds long for normalintervals when there is no phase change applied to the carrier signal Bat the transmitter. However, at time T1, when there is a 1-to-0transition in the data waveform A, there is a corresponding lengtheningof the duration of the intermediate frequency signal D to approximately625 nanoseconds. Further, by inspection it can be seen that at theinstant T2 when the data waveform A transitions from a binary 0 to abinary 1, the intermediate frequency waveform D has the duration of itsperiod reduced to approximately 375 nanoseconds. In accordance with theinvention, the demodulator circuit 122 of FIG. 3 will detect theoccurrence of changes in the duration of the intermediate frequencysignal D and will correctly reconstruct the data waveform as the outputsignal A'. The modulation could be done in the opposite manner, forexample, by applying a phase shift delay when the binary input waveformA rises from a 0 value to a 1 and removing the phase shift delay whenthe binary value transitions from a 1 to a 0, for example.

It is seen that the circuit of FIG. 3 monitors the time intervalsbetween consecutive positive going edges of the D waveform and, inaddition, it also monitors the time intervals between consecutivefalling edges of the D waveform. In accordance with the invention, thisdual monitoring of both the positive going edges of the D waveform andthe negative going edges of the D waveform accommodates the asynchronouscharacter between the data waveform A and the intermediate frequencywaveform D. For example, if a binary 1-to-0 transition occurred in thedata waveform A at an instant close to the transition of theintermediate frequency waveform D, then the modulated character of thewaveform might be missed for the PSK measurement of the occurrence ofthat data transition; however, it would be correctly reflected in thecorresponding negative edges of the intermediate frequency waveform.Thus, by monitoring both positive edges and negative edges, it iscertain that the asynchronous transitions of the binary waveform A willhave their modulated manifestation detectable in the intermediatefrequency waveform D.

The demodulator circuit 122 of FIG. 3 takes the output D from limitamplifier 200 and applies it to the carrier sense circuit 400, which isshown in greater detail in FIG. 4. The carrier sense circuit 400correctly detects the presence of the carrier signal bearing a 2 MHzmodulated intermediate frequency signal, and outputs a signal CRSrepresenting a successful detection of the carrier signal. This isoutput to the frequency compensation circuit 500, shown in FIG. 5.

The output D from the limit amplifier 200 in FIG. 3 is also applied tothe digital filter and intermediate frequency edge detector 600, shownin FIG. 6. The circuit of FIG. 6 correctly detects a positive going edgeof the intermediate frequency waveform. This signal is applied as POS EDas the positive edge detection signal to the positive edge datademodulator 700, shown in FIG. 7. The digital filter and intermediatefrequency edge detector circuit 600 of FIG. 6 also correctly detects anegative going edge of the intermediate frequency waveform. Thisrecognition is output as the signal NEG ED to the negative edge datademodulator circuit 800 of FIG. 8.

The positive edge data demodulator circuit 700 of FIG. 7 correctlyidentifies a short duration interval between consecutive positive edgesof the intermediate frequency waveform D, which represents a transitionfrom a binary 0 to a binary 1 for the data waveform A. This informationis output as the signal POS T1 to the digital filter and data outputcircuit 900 of FIG. 9. The positive edge data demodulator circuit 700 ofFIG. 7 also correctly detects a long duration interval betweenconsecutive positive intermediate frequency edges for the waveform D,and outputs this recognition as the signal NEG T1 to the digital filterand data output circuit 900 of FIG. 9. The frequency compensationcircuit of FIG. 5 outputs signals FC0, FC1, and FC2 to the positive edgedata demodulator circuit 700 of FIG. 7, for the purpose of applying adigital offset to the circuit 700 to compensate for changes in thefrequency of the nominally 2 MHz frequency for the intermediatefrequency signal D. When the system is in a carrier sense measurementmode, if the duration interval between positive edges of theintermediate frequency waveform D is not within a specified range,positive edge data demodulator circuit 700 generates a signal (RST CRS)that resets the carrier sense circuit 400 and restarts a carrier sensemeasurement. If the duration of a cycle while in this mode varies morethan a predetermined amour from cycle to cycle of the intermediatefrequency signal, then the positive edge data demodulator circuit 700generates another signal that resets the carrier sense circuit 400 andrestarts a carrier sense measurement.

The negative edge data demodulator circuit 800 correctly detects theshort duration between consecutive negative edges of the intermediatefrequency signal D and outputs a recognition signal POS T2 to thedigital filter and data output circuit 900 of FIG. 9. The negative edgedata demodulator circuit 800 of FIG. 8 also correctly detects theoccurrence of long duration intervals between consecutive negative edgesof the intermediate frequency signal D, outputting the recognitionsignal NEG T2 to the digital filter and data output circuit 900 of FIG.9. The frequency compensation circuit of FIG. 5 outputs the signals FC0,FC1, and FC2 to the negative edge data demodulator circuit 800 of FIG. 8to apply a digital offset to the circuit 800 to compensate forvariations in the nominal 2 MHz frequency of the intermediate frequencysignal D.

The digital filter and data output circuit 900 of FIG. 9 correctlyoutputs the reconstructed binary value A' of the digital data waveformA. The circuit 900 of FIG. 9 applies a digital filter to prevent ringingof the input signal from being misinterpreted as date for the outputsignal. The reconstructed signal A' is output on line 123 from thedemodulator 122 to the local area network interface adapter 124. Thedigital filtering function performed by the circuit of FIG. 9 monitorsbinary 0 to binary 1 transitions, and binary 1 to binary 0 transitionsof the data waveform A, and blocks the recognition of any further binarydata transitions in waveform A for a subsequent 800-nanosecond interval.This is done to prevent spurious ringing signals from confusing thecircuitry during the 800-nanosecond interval following a valid datatransition in waveform A.

In this manner, the invention successfully accomplishes the detection ofthe intermediate frequency signal on the 2.4 GHz carrier, itsuccessfully applies frequency compensation to overcome a carrierfrequency drift, and it successfully demodulates the intermediatefrequency signal to reconstruct the binary digital waveform.

Reference to FIG. 1A will show the intervals between consecutive risingedges of the waveform D, represented as R, and the intervals betweenconsecutive falling edges of the waveform D, represented as F. It can beseen that the intervals between rising edges R are four consecutiveperiods of 500 nanoseconds for normal intervals, followed by a longinterval of 625 nanoseconds at the time T1 when the transition from abinary 1 to a binary 0 occurs for the data waveform A. This is followedby two 500 nanosecond periods which are normal, followed by a shortperiod of 375 nanoseconds, the duration of which is cut short by theoccurrence at time T2 of the transition from a binary 0 to a binary 1for the data waveform A. T2 is then followed by two more normalintervals R of 500 nanoseconds between the rising edges of D.Correspondingly, the falling edge of the waveform D represented by theintervals F in FIG. 1A, shows three consecutive intervals of 500nanoseconds for the normal intervals, followed by a long interval of 625nanoseconds which spans the instant of time T1. This is followed bythree consecutive normal intervals of 500 nanoseconds and then a shortinterval of 375 nanoseconds which spans the instant of T2. This is thenfollowed by a normal interval of 500 nanoseconds. The invention is ableto identify these normal, long and short intervals for both the risingedge and falling edge of the waveform D, and to correctly infer andreconstruct the data waveform A, as the reconstructed waveform A'.

FIG. 4 is a more detailed illustration of the logic for the carriersense circuit 400. FIG. 10 shows a diagram for the carrier sense timing.The 2 MHz intermediate frequency signal D is input on line 201 to latch402. Latch 402 is connected to latch 404 and to latch 405. The output oflatch 404 and the inverted output of latch 405 are applied to AND gate406. Gate 406 outputs a signal for every positive edge detected for theinput waveform D. The output of AND gate 406 is 2 MHZ EDG and is appliedto counter 424 which counts the 2 MHZ EDG signal. Counter 424 has fouroutput decodes set to go high after the respective durations shown inthe figure. The output CS=5 of counter 424 is applied to an input ofAND-OR gate 426. The output of AND-OR gate 426 is applied to the R inputof latch 427 and to the R input of latch 428. The output CS=10 isapplied to the S input of latch 427. Output CS=74 is applied to the Sinput of latch 428. Output CS=75 is applied to an input of AND-OR gate422. The signal IN₋₋ WIN, generated by the positive edge datademodulator circuit 700 is applied to another input of AND-OR gate 422.The output of AND-OR gate 422 is applied to the synchronous reset inputSR of counter 424. The signal RST CRS, output from OR gate 727 inpositive edge data demodulator circuit 700, resets the count of counter424 during a carrier sense measurement when the measured duration of acycle of the intermediate frequency waveform D exceeds a predeterminedtolerance for the duration of one cycle of the intermediate frequency atthe nominal center frequency. When enabled, counter 424 countsconsecutive occurrences of intermediate frequency waveform, and if itsuccessfully counts to 10, frequency compensation circuit 500 is enabledvia the GOOD and /GOOD outputs of latch 427. If counter 424 successfullycounts to 74, the carrier sense signal CRS indicating that the carrierhas been detected is output via latch 428. The signal CRS is thenapplied to the LAN interface adapter 124 of FIG. 2 to signal thereceiving node to begin looking at the data content of the demodulatedoutput waveform A'. At count 75, the =75 output signal is applied to ANDgate 422. Counter 424 is reset and made ready for detecting a loss ofthe carrier.

The frequency compensation circuit 500 of FIG. 5 includes the counter502, which is a 7-bit counter that counts down. The counter counts the13.5 MHz clock pulse and is enabled by the ANDing of signals GOOD and/CRS. The counter 502 counts how long it takes to successfully detect 64consecutive intermediate frequency cycles of the D waveform. If theintermediate frequency D waveform is exactly 2 MHz in frequency, thenthe outputs from the counter 502 will be FC0=0, FC1=0, and FC2=0. If ittakes a longer time than nominal to count 64 consecutive IF cycles, thenthe actual frequency of the intermediate frequency waveform D is lessthan 2 MHz and the values of FC0, FC1 and FC2 will apply a negativeoffset to the counters 702 and 802 in FIGS. 7 and 8. Conversely, if ittakes less than the nominal duration of time to count 64 consecutive IFsignals in the counter 502 of FIG. 5, then the values of FC0, FC1 andFC2 will provide a positive offset, reflecting that the actual frequencyof the intermediate frequency waveform D is higher than the nominal 2MHz. This positive offset is then applied to the counter 702 in FIG. 7and counter 802 in FIG. 8. The counter 502 in FIG. 5 has as one inputthe /GOOD input and that is the output F from the good latch 427 in FIG.4. When the /GOOD input is active at the counter 502, the counter haspre-loaded a hex value of 38 hex or a decimal value of 56 into thecounter. If the nominal 2 MHz frequency currently exists for the IFwaveform D, then the counter 502 will count down for 64 cycles of the IFwaveform, and this will take 32 microseconds. This would correspond to432 counts of the 13.5 MHz clock applied to the counter 502. Since thecounter 502 is a 7-bit counter, it will wrap three times in countingdown from the preloaded value of 56, and the resulting value in the7-bit counter will be a value of 8. Since FC0, FC1 and FC2 are the highorder bits of the 7-bit counter, their values will be 0, 0, and 0,respectively, for this condition. Alternately, if the IF frequency islow, then the counter 502 will count more than the nominal 432 countsand as the counter counts down, the next 8 counts of the 13.5 MHz clockit will wrap. As this occurs, all binary 1's will exist in the 7 bits ofthe counter. This corresponds to a signed binary value of -1. Thus, thevalues of FC0, FC1 and FC2, when they are all 1's, corresponds to avalue of -1. This negative value is then applied as a negative offset tothe counters 702 in FIG. 7 and 802 in FIG. 8. Alternately, if the IFfrequency is higher than the nominal 2 MHz, then the counter 502 willnot completely count the 432 counts corresponding to a nominalfrequency. There will thus be a corresponding positive binary value forFC0, FC1 and FC2, and this will be applied as a positive offset to thecounter 702 in FIG. 7 and the counter 802 in FIG. 8.

FIG. 6 is a detailed logic block diagram of the digital filter andintermediate frequency edge detector circuit 600. The waveform D isinput on line 201 to the D input of the latch 602, and the 54 MHz clockpulse is applied to the C input. The N output is connected to the Dinput of the latch 604, and the 54 MHz clock signal is applied to the Cinput of the latch 604. The N output of the first latch 602 is appliedto one input of the AND gate 606, and the F output of the second latch604 is applied to the second input of the AND gate 606. When both inputsto the AND gate 606 are high, that indicates that a positive going edgehas been detected. The third input to the AND gave 606 is part of thedigital filter which avoids the detection of false positive datatransitions. If the actual data waveform A is a binary 1, and if anotherpositive edge is detected before 422 nanoseconds, then the circuitignores a rising edge detection. The AND gate 608 has as one input thesignal RCV DTA which is output from the latch 918 in FIG. 9. This signalis the main output of the demodulator 122 and is high when the datawaveform A' is high and is 0 when the data output for A' is 0. The otherinput to the AND gate 608 is LPOS ED which is the output of the latch616 in FIG. 6. If both of these signals are high, the AND gate 608 setsthe latch 612 and the corresponding output from the N terminal of latch612 is applied through the inverter 614 to a third input of the AND gate606. This disables the AND gate 606 and prevents a signal being appliedto the D input of the output latch 616. This digital filtering operationavoids the recognition of false positive data. Correspondingly, the ORgate 610 has the signal LPOS 15 applied to one input, which comes fromthe register 706 of FIG. 7. The other input to the OR gate 610 is LPOSED which is the output of the latch 616 of FIG. 6. The output of the ORgate 610 is applied to the reset of the latch 612.

One aspect of the digital filter and IF edge detector 600 of FIG. 6 isthe digital filtering feature which prevents a false detection of a datasignal for waveform A. In FIG. 6, the AND gate 608 has as one of itsinputs the RCV DTA input, which is the reconstructed waveform A' outputfrom the circuit of FIG. 9. When the reconstructed waveform A' has abinary 1 value, the digital filter in FIG. 6 blocks any indication thata transition from a binary 0 to a binary 1 is taking place with thewaveform A. This transition would not take place if there is a validcurrent binary 1 state for the waveform A and its correspondingreconstructed waveform A'. Thus, once a latched positive signal isoutput from the latch 616 in FIG. 6, it is applied as one input to theAND gate 608 and the received data signal RCV DTA, which is high, isapplied to the other input of the AND gate 608. This sets the S inputfor the latch 612. The latch 612 is thus set on every positive edge ofthe IF signal for as long as there is a binary 1 state for the value A'waveform. The output of the latch 612 is inverted through the inverter614 and applied to one of the three inputs of the AND gate 606. Thus, ifthe latches 602 and 604 apply positive inputs to the AND gate 606indicating that a positive edge has been detected for the IF waveform D,the AND gate 606 will only be enabled if the received data value is low.If the received data value is high, then the input to the AND gate 606is not enabled until the latch 612 is reset. The latch 612 is not resetuntil the latched positive 15 signal from counter 702 is applied throughthe OR gate 610 to the reset input of the latch 612. The LPOS 15 signalfrom the counter 702 does not go high until 422 nanoseconds after theoccurrence of the positive edge LPOS ED output from the latch 616. Thus,it is seen that for an interval of 422 nanoseconds following theoccurrence of LPOS ED that the LPOS ED output will be disabled. This ineffect blocks the recognition of any short interval between consecutiverising edges of the IF waveform D, which would erroneously correspond toan erroneous indication of a rising data waveform signal from A=0 toA=1. A similar operation takes place for the circuit driving the ANDgate 628 into the latch 630 for the negative edge detection circuitry ofFIG. 6. Turning to FIG. 1A, the diagram of the IF signal waveform Dshows at the beginning of time T1 that the IF waveform is phase delayedby 90°. The design of the receiver 116 includes a low pass filter tominimize overlapping cross-talk from nearby channels. A low pass filter150 filters the IF output from the mixer 120 before it is applied to thedemodulator 122 in FIG. 2. The purpose of the low pass filter is toblock out nearby IF channels in a frequency multiplexed application. Inparticular, where frequency hopping is performed between nearby IFbands, each of which is 1 MHz wide, it is important to eliminatecross-talk from such nearby channels. As a consequence of such low passfiltering when a 90° phase delay is applied, such as at time T1, ifthere were no low pass filter the waveform immediately following T1 forwaveform C would be relatively flat. However, because of the low passfilter and the elimination of high frequency components in the waveformC, the waveform appears to have a small peak above 0 and a small valleybelow 0 immediately following the time T1. When the limit amplifier inFIG. 3 is applied to the waveform C', it amplifies the small peak andthe small valley in the waveform C' to get a distinct spurious squarewave following the time T1. This square wave must be blocked from beinginterpreted as an indication of a valid transition of either a risingedge or a falling edge for the IF waveform. This is done by the digitalfiltering circuitry of FIG. 6. Attention is directed to the latch 612waveform shown in FIG. 1A, which indicates the binary state of the latch612 in the digital filter of FIG. 6. The latch 612 is seen to stay in anon state for a period of 422 nanoseconds. The 422 nanosecond duration ofthe on state for the latch 612 prevents the circuit of FIG. 6 fromrecognizing the negative edge and following positive edge immediatelyafter T1 as being valid edges for the IF waveform. In this manner, thedigital filter compensates for the necessity of applying low passfiltering to the IF waveform to avoid overlapping adjacent channels in afrequency hopping application. Note that after latch 918 falls, as isshown in the waveform of FIG. 1A, latch 612 no longer is set and this isreflected in the waveform for latch 612 also shown in FIG. 1A. Not untilthe waveform A rises again at time T2 will latch 918 become set andcorrespondingly latch 612 periodically set to once again apply thedigital filtering to the IF waveform to ignore the spurious pulses dueto the low pass filtering of the IF waveform.

A similar operation occurs for the negative edge detection portion ofthe circuit 600 of FIG. 6 AND gate 620 has the input signals RCV DTA andLNEG ED. The output of the AND gate 620 is applied to the set input ofthe latch 624. The latch 624 is clocked with a 54 MHz clock. The otherinput to the latch at the reset input is from the OR gate 622 which hasthe input LNEG 15 which comes from the counter 806 in FIG. 8. The otherinput to the OR gate 622 is LNEG ED. The output of the latch 624 isapplied through an inverter 626 to one input of the AND gate 628. The Foutput of latch 602 is applied to a second input of the AND gate 628 andthe N output of the latch 604 is applied to the third input of the ANDgate 628. The AND gate 628 is enabled whenever a falling edge isdetected for the intermediate frequency waveform D. This is output tothe D input of the latch 630 which is clocked at 54 MHz and provides theoutput signal LNEG ED representing the falling edge having beendetected. The signal LPOS ED is applied the counter 702 of FIG. 7 forpositive edge data demodulation and the signal LNEG ED is applied to thecounter 802 of FIG. 8 for negative edge data demodulation.

FIG. 7 shows a logic block diagram for the positive edge detection datademodulation circuit 700. The counter 702 counts up the 54 MHz clockpulses applied at input C. The LPOS ED signal, representing a positiveedge detection for the IF waveform D, is applied to the counter anddigital offset values FC0, FC1 and FC2 are applied from the frequencycompensation circuit of FIG. 5. Counter 702 has 6 Q outputs that areapplied to the D inputs of register 720. The Q outputs of latch 720 areapplied to the D inputs of latch 721. Both latch 720 and 721 are clockedby the 54 MHZ clock signal and both are enabled by the LPOS ED signaloutput by latch 616 of circuit 600 of FIG. 6. The Q outputs of latch 720are applied to the input of decoder 725 and to the A inputs of dataselector 722. The output of decoder 725 is inverted and applied to aninput of AND-OR gate 726. The Q outputs of latch 721 are applied to oneinput of adder 723. The outputs of adder 723 are applied to the inputsof AND-OR gate 724.

When looking for a carrier sense condition, latch 616 of circuit 600 inFIG. 6 develops a gating pulse LPQS ED of 18.5 ns duration used to gatethe measurement of the IF period. Counter 702 is initially loaded withzeros at the occurrence of LPOS ED. Counter 702 then counts up with the54 MHZ clock until the next LPOS ED pulse is generated. The occurrenceof the second LPOS ED pulse loads registers 720 and 721 and initializescounter 702 with zeros. Register 720 contains a measured value for thetime period of one cycle of the IF signal. If the value in register 720is not within the range hex 16 to hex 1D, that is, within the range of407 ns to 556 ns (500 ns nominal) decoder 725 causes the signal RST CRSto be generated via AND-OR gale 726 and OR gate 727. When RST CRS isgenerated, the measurement of the IF period is restarted by resettingcounter 424, which in turn clears latches 427, 428 and, 429. If thevalue in register 720 is within about 50 ns of the nominal time periodfor 1 cycle of a nominal 2 MHz IF signal, that is, within hex 16 to hex1D, the signal RST CRS is not generated and counter 424 is not reset.

On subsequent successive cycles of the intermediate frequency signal,adder 723 makes a comparison of the values stored in registers 720 and721 since the signal CRS is not active and the B inputs to data selector722 are not selected. As long as the values stored in registers 720 and721 are within less than 2 counts of each other, that is, less thanabout 36 ns different, then the signal IN₋₋ WIN is generated via AND-ORgate 724. Counter 424 continues to count cycles of the IF signal untilit counts 10 cycles that are within the range of decoder 725 and aresimultaneously less than two counts for consecutive cycles, that is,having a delta of less than 2. At a count of 10 cycles, frequencycompensation circuit 500 of FIG. 5 is enabled via the GOOD and /GOODoutputs of latch 427. If the IN₋₋ WIN output goes inactive, meaning thatthe difference between the values stored in registers 720 and 721 wastwo or greater, counter 424 resets via the sub-portion C of AND-OR 422.If the delta between the values stored in registers 720 and 721 remainsless than two for 74 consecutive IF pulses, latch 428 is set, indicatingthat a valid carrier sense indication, or condition, has been detected.On the next IF cycle, that is, cycle 75, counter 424 is reset to zerovia AND-OR gate 422 sub-portion A and latch 429 is set, indicating thatthe carrier sense measurement is complete. The CRS signal is output tothe media access logic of the system by latch 428 for execution of acollision avoidance algorithm.

The carrier sense circuitry of circuits 700 and 400 are now in a mode oflooking for a valid end in the carrier sense indication. This isaccomplished by looking for a nominal IF cycle to occur at least oncefor every five cycles of the waveform D in FIG. 1. The circuitry thataccomplishes this measurement is via data selector 722. When the signalCRS is generated, the B inputs to selector 722 having a valuecorresponding to the time period for one nominal cycle of the IF signal,for example, hex 19, are selected. The value in register 721 is thencompared by adder 723 to the value applied to the B inputs of selector722. The output IN₋₋ WIN becomes active anytime that the value inregister 721 is within 3 counts of the value applied to the B inputs ofselector 722.

Since counter 424 was reset at the count 75 and is now able to count upagain, the IN₋₋ WIN output must reset counter 424 via AND-OR gate 422sub-portion B at least once every 5 IF cycles. If this happens, thecarrier sense indication will be maintained. Otherwise, if counter 424is not reset, the =5 output of counter 424 will reset latches 427 and428 via AND-OR gate 426. This causes the CRS signal to become inactive,indicating loss of the carrier sense condition. The inactive CRS signalis used by the medium access control logic in the collision avoidancealgorithm, enabling the node to now transmit data to another node. Thecarrier sense circuitry is ready to detect another valid carrier sensecondition.

The counter 702 also has four decoded outputs, the first output 8represents a 200 nanosecond duration, the output 15 represents a 426nanosecond duration, the output 1B represents a 574 nanosecond duration,and the output 29 represents a 796 nanosecond duration. These decodedsignals from the counter 702 are applied through the staging logic 704.The AND gate 704 is four two input AND gates, with one of the inputsbeing the not positive edge signal and the other input of the AND gatebeing from each of the respective decoded outputs shown for the counter702. The output of the AND gate 704 is applied to the input of thestaging register 706. The net effect of the AND gate 704 and the stagingregister 706 is to properly stage the outputs of the counter 702 so thatthey can be appropriately applied to the following logic circuitry inFIG. 7. Similar comments can be made for the AND gate 804 and stagingregister 806 of FIG. 8.

The output of the gate 704 is then applied to the register 706 which isclocked at 54 MHz and provides a staging operation for the decodedsignal lines output from the counter 702. The decoded signal lines arethen output from the register 706 and applied as follows. The 204nanosecond output decode 8 is applied to the set input of the latch 712.The 426 nanosecond output 15 from counter 702 is applied through the ORgate 708 to the reset input of the latch 712. The other input to the ORgate 708 is the LPOS ED signal. The output of the latch 712 is thewindow latch and it is applied to the D input of latch 716. The outputof latch 716 is POS T1 and represents the detection of a short intervalbetween consecutive positive edges of the waveform D, corresponding to a0-to-1 transition of the data waveform A. The 1B output which is the 574nanosecond decode output from counter 702 is applied through register706 to the set input of the latch 714 and the 796 nanosecond decodedoutput 29 from the counter 702 is applied through the register 706 andthe OR gate 710 to the reset input of the latch 714. The other input tothe OR gate is LPOS ED. The output of the latch 714 is applied to the Dinput of the latch 718 whose output is NEG T1. This signal representsthe detection of a long duration between consecutive positive edges ofthe input waveform D, which corresponds to a 1-to-0 transition for thebinary data waveform A. The POS T1 output from latch 716 represents ashort duration of between 200-422 nanoseconds. The output NEG T1 fromlatch 718 represents a long duration of from 568 to 800 nanoseconds.These signals are applied to the digital filter and data output circuitof FIG. 9.

FIG. 8 is organized in a manner similar to that shown for FIG. 7.Counter 802 receives NEG ED signal, the FC0, FC1 and FC2 signals, andcounts a 54 MHz clock. It outputs 200, 422, 568 and 800 nanoseconddecoded signals which are applied through the logic 804 and the register806 to the latch 812, the OR gate 808, the latch 814 and the OR gate810. The output of the latch 812 is applied to the D input of the latch816, whose output is POS T2 which represents the detection of a shortduration between consecutive negative edges of the input waveform D. Theoutput of latch 814 is applied to the D input of the latch 818 whichoutputs the signal NEG T2. This signal represents detection of a longduration between consecutive negative edges of the input waveform D. Ashort duration for POS T2 indicates a transition of the data waveform Afrom binary 0 to binary 1. A long duration represented by NEG T2represents a binary transition from a binary 1 to a binary 0 for thedata A. These signals are applied to the digital filter and data outputcircuit 900 of FIG. 9.

FIG. 9 shows the register 902 which receives these signals and outputsthem through the OR circuits 904 and 906. The latch 908 is connected tothe AND gate 912 which is satisfied when a short transition signal isreceived, of the waveform D. The output of the AND gate 912 sets theoutput latch 918 for RCV DTA, indicating that a transition from binary 0to binary 1 has been detected. OR 906 is output to latch 910 and ANDgate 914. AND gate 914 is satisfied when a long duration signal isreceived. The output of the AND gate 914 is to the reset input of thelatch 918.

The register 902 in FIG. 9 has the long duration signals NEG T1 and NEGT2 applied through the register 902 and OR gate 906 to the AND gate 914and the latch 910. When a negative edge is detected, either for thenegative edge detector or for the positive edge detector, then the ANDgate 914 is satisfied and resets the latch 918. The output RCV DTA thengoes from 1 to 0, which reconstructs the binary 1 to binary 0 transitionof the data waveform A. The latch 910 has an output from its N terminallabelled LNTRAN. The AND gate 912 in FIG. 9 has an output applied to theAND-OR gate 920, which has another output to its AND gate applied fromthe enable data signal EN DTA. This signal comes from the output latch924 in FIG. 9, and is used in the digital filter feature of this circuitwhich prevents ringing signals from being detected. The other input tothe OR gate of the gate 920 is a signal 26 output from the counter 922.

The output of the gate 920 is applied to the reset terminal of thecounter 922. The counter 922 counts up and counts 13.5 MHz clock pulses.It has a 14-15 output which is applied to the set input of the latch924. The latch 924 has a clock input from the 13.5 MHz clock. It has areset input RSTRC from AND gate 920. The output of the latch 924 is ENDTA which represents the period following a 1.11 millisecond interval,after which valid signals may be detected.

FIG. 11 is a timing diagram of the data demodulation. The NEG windowwaveform pertains to the latch 714. The POS window waveform pertains tothe latch 712. In FIG. 11, the L waveform corresponds to the latch 602and the L2 waveform corresponds to the latch 604 in FIG. 6. The NEGwindow waveform corresponds to the latch 714 in FIG. 7 and the POSwindow waveform corresponds to the latch 712 in FIG. 7.

FIG. 12 is a logic diagram illustrating how the 54 MHz local clock pulseis counted down to provide 27 MHz and 13.5 MHz clock pulses which areused in the logic circuits.

Table 1 shows the frequency compensation count values for the counter502 in FIG. 5. The counter 502 counts the 13.5 MHz clock pulses for 64consecutive cycles of the IF waveform in order to measure the actualfrequency of the IF waveform. Table 1 shows several columns; the firstcolumn is the number of 13.5 MHz clock pulses that have been countedfrom the beginning of the counting interval for the counter 502. Thetable goes from 1count all the way up to 505 counts. This is based uponlocal crystal oscillators at the transmitter and the receiver, eachhaving a frequency of 2.4 GHz for the transmitter ±50 parts per millionand 2.4 GHz+2 MHz±50 parts per million. In the worst case, thetransmitting crystal oscillator could have its tolerance in the oppositedirection from the crystal oscillator at the receiving node and thiswould result in there being a ±240 KHz tolerance in the differencebetween the frequencies for the transmitting oscillator and thereceiving oscillator. This then would correspond to a counting range offrom 378 clock counts for 64 IF cycles, corresponding to a 27.93microsecond duration for 64 IF cycles, up to 504 clock counts for 37.26microseconds required to count the 64 IF cycles. The first column ofTable 1 is the number of counts of the counter, the second column is theinitially-set count applied as the AL count in FIG. 5. If the counterwere a 9-bit counter, then 440 counts would correspond to thehexadecimal number 1B8 hex. For an 7-bit counter, the hexadecimalrepresentation is 38 hex. Since the counter 502 is an 7-bit counter, thevalue of 38 hex is loaded into the counter 502 at the beginning of thecounting period. Taking the top three bits in an 7-bit counter as FC0,FC1 and FC2, they would represent a binary value of 3 for a startingcount of 440 for the first pulse counted of the 13.5 MHz clock. Thethird column of Table 1 shows the hexadecimal value for a 9-bit counter,the fourth column shows the hexadecimal representation in an 7-bitcounter. The fifth column the value of the binary representation forFC0, FC1 and FC2 and the sixth column represents the time in nanosecondswhich is the duration from the beginning of the clock pulse counting.Table 1 shows the progression of the values for these six columns as thenumber of 13.5 MHz clock pulses increases from 1 up through 378. At thelevel of the 377 counted clock pulse, the remaining count in the counter502 is 64 and this corresponds to a hexadecimal representation of 40 forboth a 9-bit counter and an 7-bit counter. The corresponding binaryvalue for FC0, FC1 and FC2 would be a value of 4 and this would be atthe 27852 nanosecond duration since the beginning of the clock countingperiod. At this point, the IF frequency is 2.292 MHz and thiscorresponds to a 27925 nanosecond interval since the beginning of theclocking. Table 1 shows some additional columns. The POS window startvalue and stop value refer to the latches 712 and 812 in FIGS. 7 and 8.The NEG window start and stop values refer to the latches 714 and 814 inFIGS. 7 and 8. Table 1 shows that the binary value for FC0, FC1 and FC2will slowly decrease from a value of 4 at 27926 nanoseconds or an IFfrequency of 2.292 MHz to 0 at a value of 2.000 MHz. This is the normalor nominal value for the IF frequency. As the IF frequency continues todecrease, at a value of 1.959 MHz, it is seen that the binary value ofFC0, FC1 and FC2 goes negative. The negative value continues tonegatively increase up to a value of 4 at the lower range for the IFfrequency of 1.718 MHz. The values for FC0, FC1 and FC2 are applied asoffset values to the counters 702 and 802 in FIGS. 7 and 8, aspreviously discussed. Thus, it is seen that frequency compensation isaccurately imposed by the invention.

A problem occurs with carrier detection when the transmitter isstabilizing its frequency at the beginning of a transmission interval.The transmitter will change its transmission frequency each time thereis a frequency hopping event in the network. In addition, the frequencyof transmission is different from the local oscillator receivingfrequency, and therefore every time a node in the local area networkchanges from the receiving mode to the transmitting mode, the oscillatorfrequency must stabilize at the transmitting frequency. During theinterval of stabilization of the transmitting frequency, any receiver inthe network that detects the presence of the carrier signal beingtransmitted by the transmitter, risks performing a carrier detection onan unstable signal. This problem is solved by the intentionalintroduction of a spoiler signal at a transmitter during an initialperiod when the transmitter is attempting to stabilize a newtransmission frequency. Thus, during that initial period of attemptedstabilization by the transmitter, any receiver detecting the transmittedcarrier signal will not have a successful carrier detection operation.It is only after the transmitter has stabilized its signal that thespoiler signal is removed from modulating the carrier from thetransmitter to permit receivers to successfully detect the stabilizedtransmitted carrier signal.

FIG. 13 illustrates the local area network shown in FIG. 2, but with theaddition of the carrier detection spoiler signal generator 170 at thetransmitter sending node 110. The source computer 102 outputs on line171 the information as to whether the node is in a transmitting mode ora receiving mode. When the source computer 102 in FIG. 13 begins thetransmitting mode, a signal is applied on line 171 to the oscillator 100to begin the attempt to stabilize the new transmitting frequency. Thesignal 171 is also applied to the carrier detection spoiler signalgenerator 170, to start the spoiler signal SP which is applied to themodulator 106.

FIG. 14 shows a more detailed view of the carrier detection spoilersignal generator 170. The start transmission signal 171 is applied to a100 microsecond timer 172 which turns on the enabling line 173. Alsoincluded in the carrier detection spoiler signal generator 170 is a 250KHz signal generator 174. A 250 Kbps pulse train is output on line 175.Lines 173 and 175 are applied to the AND gate 176, the output of whichis the spoiler signal SP. At the instant that the signal on line 171 isapplied to the timer 172, the enabling signal 173 is applied to the ANDgate 176. For a duration of 100 microseconds, the AND gate 176 isenabled, and passes the 250 KHz pulse train on line 175 out as thespoiler signal SP. The duration of 100 microseconds for the timer 172was determined from the maximum normal time required for a transmitteroscillator 100 to stabilize at a new transmission frequency. Othervalues could be chosen for the 100 microsecond timer 172. The 250 KHzsignal output on line 175 and passed as the spoiler signal SP to themodulator 106 produces a modulation phase change in the carrier signal Coutput from the modulator 106. The occurrence of the modulated phasechange is once every four IF intermediate frequency intervals which areeach 500 nanoseconds long.

Reference to FIG. 15A will show a sequence of the intermediate frequencypulses D which also were shown in FIG. 1A. At the receiver, the mixer120 mixes the local oscillator 118 signal B' with the received carriersignal C, producing the D waveform. The D waveform shown in FIG. 15A isseen to have a phase modulation occur at every eighth intermediatefrequency pulse. As was discussed above, the carrier sensing circuit 400counts 32 consecutive IF pulses on the waveform D before it outputs thesignal CRS indicating that a successful detection of the carrier hasbeen made. In accordance with the invention, by intentionally spoilingthe carrier signal C through the intentional introduction of a phasechange in one out of eight IF pulses on the waveform D by using thecarrier detection spoiler signal generator 170 at the transmitter, thecarrier sense circuit 400 at the receiver is not capable of successfullyidentifying the presence of a carrier. In accordance with the invention,it will not be until 100 microseconds after the beginning of thetransmission interval at the transmitter, that the spoiler signal SPwill stop modulating the carrier signal being sent to the transmitter tothe receiver. Thus, the receiver is prevented from successfullyperforming a carrier detection operation on the signal transmitted fromthe transmitter, until 100 microseconds after the transmitter begins itstransmission interval, which is sufficient time to enable thetransmitter's oscillator 100 to stabilize at the new transmissionfrequency.

FIG. 15B shows the state of the waveform D after the transmitter hassuccessfully passed its 100 microsecond duration and its transmittingfrequency has stabilized. The uniform IF pulses in the waveform D ofFIG. 15B will enable the carrier sensing circuit 400 of the receiver tosuccessfully identify the presence of the carrier and output the signalCRS, as described above.

Reference is now made to FIG. 16 which shows a consolidated node in thelocal area network of FIG. 13, which includes both a transmitter andreceiver portion. It is seen in FIG. 16 that a single oscillator 100 isused to generate both the transmission frequency as well as thereceiving frequency for the mixer 120. The oscillator frequency from theoscillator 100 is increased by 2 MHz before it is applied to the mixer120 for receiver operations. A node computer 102' will apply atransmission control signal TX to the gate 177 to apply the 2.4 GHztransmission signal from oscillator 100 to the modulator 106. If thecomputer 102' is in a receive mode, then it applies a receive controlsignal RCV to the gate 178 which applies the 2.4 GHz signal plus 2 MHzto the input of the mixer 120.

It is seen in FIG. 16 that the transmit signal TX is applied as a signalon line 171 to the spoiler circuit 170. FIG. 16 also shows a 200millisecond timer 188 which serves to identify the frequency hoppinginterval for the network of FIG. 13. In the network of FIG. 13, eachsending node and receiving node will cooperatively change its frequencyfor transmission and reception every 200 milliseconds, in a operationknown as frequency hopping. The 200 millisecond timer 188 notifies thecomputer 102 prime of each new frequency hopping interval.

FIG. 17 shows the format of the message 180 which is transmitted overthe radio link 115 in the network shown in FIG. 13. The message 180includes the header portion 182, the data portion 184, and the trailerportion 186. The message 180 trailer portion 186 includes a frequencyhopping sequence F1, F2, F3 and F4. The various communicating nodes inthe network of FIG. 13 will broadcast to each other every 200millisecond frequency hopping interval a new message 180 whichidentifies the next 4 consecutive frequency hopping frequencies for eachof the next 4 frequency hopping intervals that will occur.

Each time a transmitter at a communicating node in the network shown inFIG. 13 either changes its status from receiving to transmitting so thatthe transmitter must stabilize a new transmission frequency, it willundergo the carrier detection spoiler signal generation operationdescribed above. In addition, every time a communicating node performs afrequency hopping transition at the beginning of a new frequency hoppinginterval, then the transmitter will begin transmitting at a newfrequency which requires stabilization, and therefore the transmitteronce again will undergo the carrier detection spoiler signal generationoperation described above.

In this manner, receivers in the network of FIG. 13 are prevented fromerroneously identifying carrier signals whose frequencies have not yetstabilized.

Table 1 is attached which consists of four pages labeled Table 1(1),Table 1(2), Table 1(3) and Table 1(4).

Although a specific embodiment of the invention has been disclosed, itwould be understood by those having skill in the art that changes can bemade to that specific embodiment without departing from the spirit andthe scope of the invention.

    __________________________________________________________________________    COUNTER 502        Count  Count                   FC        | 9 |               | 7 |                   |2:0 |                      Time    Counts        | Bit|               |Bit|                   |  |                      ns    __________________________________________________________________________    0   440 1B8               38  3  0.00    1   439 1B7               37  3  0.00    2   438 1B6               36  3  74.07    3   437           148.15    4   436           222.22    5   435           296.30    6   434           370.37    7   433           444.44    8   432 1B0               30  3  518.52    9   431 1AF               2F  2  592.59    10  430           666.67    11  429           740.74    12  428           814.81    13  427           888.89    14  426           962.96    15  425           1037.04    16  424           1111.11    17  423           1185.19    18  422           1259.26    19  421           1333.33    20  420           1407.41    21  419           1481.48    22  418           1555.56    23  417           1629.63    24  416 1A0               20  2  1703.70    25  415 19F               1F  1  1777.78    26  414           1851.85    27  413           1925.93    28  412           2000.00    29  411           2074.07    30  410           2148.15    31  409           2222.22    32  408           2296.30    33  407           2370.37    34  406           2444.44    35  405           2518.52    36  404           2592.59    37  403           2666.67    38  402           2740.74    39  401           2814.61    40  400 190               10  1  2888.89    41  399 18F               0F  0  2962.96    42  398           3037.04    43  397           3111.11    44  396           3185.19    45  395           3259.26    46  394           3333.33    47  393           3407.41    48  392           3481.48    49  391 187               07  0  3555.56    53  387 183               03  0  3851.85    57  383 17F               7F  7  4148.15    61  379 17B               7B  7  4444.44    65  375 177               77  7  4740.74    69  371           5037.04    73  367 16F               6F  6  5333.33    77  363           5629.63    81  359           5925.93    85  355           6222.22    89  353 15F               5F  5  6518.52    93  347           6814.81    97  343           7111.11    101 339           7407.41    105 335 14F               4F  4  7703.70    109 331           8000.00    113 327           8296.30    117 323           8592.59    121 319 13F               3F  3  8888.89    125 315           9185.19    129 311           9481.46    133 307           9777.78    137 303 12F               2F  2  10074.07    141 299           10370.31    145 295           10666.67    149 291           10962.96    153 287 11F               1F  1  11259.25    157 283           11555.56    161 279           11851.85    165 275           12148.15    169 271 10F               0F  0  12444.44    173 267           12740.74    177 263           13037.04    181 259           13333.33    185 255 0FF               7F  7  13829.63    189 251           13925.93    193 247           1422.22    197 243           14518.52    201 239 0EF               6F  8  14814.81    205 235           15111.11    209 231           15407.41    213 227           15703.70    217 223 0DF               5F  5  16000.00    221 219           16296.30    225 215           16592.59                           IF Freq    229 211           16886.89    233 207 0CF               4F  4  17185.19    249 191           18370.37                           3.484    265 175 0AF               2F  2  19555.56                           3.273    281 159 09F               1F  1  20140.74                           3.086    297 143 08F               0F  0  21925.93                           2.919    313 127 07F               7F  7  23111.11                           2.769   Pos     Neg    329 111 06F               6F  6  24296.30                           2.634   Window  Window    345 95  05F               5F  5  25481.48                           2.512   Start                                        Stop                                           Start                                                Stop    361 79  04F               4F  4  26666.67                           2.400    375 65  041               41  4  27703.10                           2.310    376 64  040               40  4  27777.78                           2.304    377 63  03F               3F  3  21851.85                           2.298                               <- Max                                   148  370                                           519  741    379 61  03D               3D  3  28000.00                           2.286                               Comp                                   148  370                                           519  741    381 59  03B               3B  3  28148.15                           2.274   148  370                                           519  741    383 57  039               39  3  28296.30                           2.262   148  370                                           519  741    385 55  037               37  3  28444.44                           2.250   148  370                                           519  741    387 53  035               35  3  2859.59                           2.238   148  370                                           519  741    389 51  033               33  3  28740.74                           2.227   148  370                                           519  741    391 49  031               31  3  26888.89                           2.215   148  370                                           519  741    393 47  02F               2F  2  29037.04                           2.204   167  389                                           537  759    395 45  02D               2D  2  29185.19                           2.193   167  389                                           537  759    397 43  02B               2B  2  29333.33                           2.182   167  389                                           537  759    399 41  029               29  2  29481.48                           2.171   167  389                                           537  759    401 39  027               27  2  29629.63                           2.160   167  389                                           537  759    403 37  025               25  2  29777.78                           2.149   167  389                                           537  759    405 35  023               23  2  29925.93                           2.139   167  389                                           537  759    407 33  021               21  2  30074.07                           2.128   167  389                                           537  759    409 31  01F               1F  1  30222.22                           2.118   185  407                                           556  778    411 29  01D               1D  1  30370.37                           2.107   185  407                                           556  778    413 27  01B               1B  1  30518.52                           2.097   185  407                                           556  778    415 25  019               19  1  30666.67                           2.087   185  407                                           556  778    417 23  017               17  1  30814.81                           2.077   185  407                                           556  778    419 21  015               15  1  30962.96                           2.067   185  407                                           556  778    421 19  013               13  1  31111.11                           2.057   185  407                                           556  778    423 17  011               11  1  31259.26                           2.047   185  407                                           558  778    425 15  00F               0F  0  31407.41                           2.038   204  426                                           574  796    426 14  00E               0E  0  31481.48                           2.033   204  426                                           574  796    427 13  00D               0D  0  31555.56                           2.028   204  426                                           574  796    428 12  00C               0C  0  31629.63                           2.023   204  426                                           574  798    429 11  00B               0B  0  31703.70                           2.019   204  426                                           574  796    430 10  00A               0A  0  31777.78                           2.014   204  426                                           574  796    431 9   009               09  0  31851.85                           2.009   204  126                                           574  798    432 8   008               08  0  31925.93                           2.005                               < Norm                                   204  426                                           574  796    433 7   007               07  0  32000.00                           2.000   204  426                                           574  796    434 6   006               06  0  32074.07                           1.995   204  426                                           574  796    435 5   005               05  0  32148.15                           1.991   204  426                                           574  796    436 4   004               04  0  32222.22                           1.986   204  426                                           574  796    437 3   003               03  0  32296.30                           1.982   204  426                                           514  798    438 2   002               02  0  32370.37                           1.977   204  426                                           514  796    439 1   001               01  0  32444.44                           1.973   204  426                                           574  796    440 0   000               00  0  32518.52                           1.968   204  426                                           574  796    441 -1  1FF               7F  7(-1)                      32592.59                           1.964   222  444                                           593  815    443 -3  1FD               7D  7(-1)                      32740.74                           1.955   222  444                                           593  815    445 -5  1FB               7B  7(-1)                      32888.89                           1.946   222  444                                           593  815    447 -7  1F9               79  7(-1)                      33037.04                           1.937   222  444                                           593  815    449 -9  1F7               77  7(-1)                      33185.19                           1.929   222  444                                           593  815    451 -11 1F5               75  7(-1)                      33333.33                           1.920   222  444                                           593  815    453 -13 1F3               73  7(-1)                      33481.48                           1.912   222  444                                           593  815    455 -15 1F1               71  7(-1)                      33629.63                           1.903   222  444                                           583  815    457 -17 1EF               6F  6(-2)                      33777.78                           1.895   241  483                                           611  833    459 -19 1ED               6D  6(-2)                      33925.93                           1.886   241  463                                           611  833    481 -21 1EB               6B  6(-2)                      34074.07                           1.878   241  463                                           611  833    463 -23 1E9               69  6(-2)                      34222.22                           1.870   241  483                                           611  833    485 -25 1E7               67  6(-2)                      34370.37                           1.862   241  463                                           611  833    467 -27 1E5               65  8(-2)                      34518.52                           1.854   241  463                                           611  833    469 -90 1E3               63  6(-2)                      34666.67                           1.846   241  463                                           611  833    471 -31 1E1               61  6(-2)                      34814.81                           1.838   241  463                                           611  833    473 -33 1DF               5F  5(-3)                      34962.96                           1.831   259  481                                           630  852    475 -35 1DD               5D  5(-3)                      35111.11                           1.823   259  481                                           630  852    477 -37 1DB               5B  5(-3)                      35259.26                           1.815   259  481                                           630  852    479 -39 1D9               59  5(-3)                      35407.41                           1.808   259  481                                           630  852    481 -41 1D7               57  5(-3)                      35555.56                           1.800   259  481                                           630  852    483 -43 1D5               55  5(-3)                      35703.70                           1.793   259  481                                           630  852    485 -45 1D3               53  5(-3)                      35851.85                           1.785   259  481                                           630  852    487 -47 1D1               51  5(-3)                      36000.00                           1.778   259  481                                           630  652    489 -49 1CF               4F  4(-4)                      38148.15                           1.770   278  500                                           848  870    491 -51 1CD               4D  4(-4)                      36296.30                           1.763   278  500                                           648  370    493 -53 1CB               48  4(-4)                      36444.44                           1.756   278  500                                           648  870    495 -55 1C9               49  4(-4)                      36592.59                           1.749   278  500                                           648  870    497 -57 1C7               47  4(-4)                      36740.74                           1.742   278  500                                           648  870    499 -59 1C5               45  4(-4)                      36888.89                           1.735   278  500                                           648  870    501 -61 1C3               43  4(-4)                      37037.04                           1.728   278  500                                           648  870    503 -63 1C1               41  4(-4)                      37185.19                           1.721                               <- Max                                   278  500                                           648  870    505 -65 1BF               3F  3(-5)                      37333.33                           1.714                               Comp    __________________________________________________________________________

What is claimed is:
 1. An apparatus for detecting a carrier signal of aphase shift keyed modulated signal, the apparatus comprising:anintermediate frequency generator receiving a phase shift keyed modulatedsignal and generating an intermediate frequency signal, and theintermediate frequency signal having rising edges and a nominal centerfrequency; an edge detecting circuit coupled to the intermediatefrequency signal and detecting consecutive rising edges of theintermediate frequency signal, two consecutive rising edges representinga time period of a cycle of the intermediate frequency signal; a firstcounter circuit responsive to the edge detecting circuit by generating aplurality of counts, each count counted by the first counter circuitbeing a number of cycles of a reference frequency signal occurringbetween two consecutive rising edges; a comparison circuit responsive tothe first counter circuit by comparing a first count of referencefrequency cycles to a second count of reference frequency cycles when adifference between an initial count of reference frequency cycles and afirst predetermined number is less than a second predetermined number,the first predetermined number representing a time period of one cycleof the nominal center frequency, the first count and the second countrespectively representing time periods of first and second cycles of apair of consecutive cycles of the intermediate frequency signal, atleast the second count occurring subsequent to the initial count, thecomparison circuit generating a difference signal when a differencebetween the first count and the second count is less than a thirdpredetermined number; and a second counter circuit responsive to thedifference signal by counting cycles of the intermediate frequencysignal and generating a carrier detect signal when a count of theintermediate frequency signal cycles equals a fourth predeterminednumber.
 2. The apparatus according to claim 1, wherein the comparisoncircuit compares the first count to the second count when the initialcount falls within a predetermined range of numbers, the predeterminedrange of numbers corresponding to a range of time periods related to onetime period of the nominal center frequency.
 3. The apparatus accordingto claim 2, wherein the apparatus is part of a receiving node of awireless local area network, the receiving node being associated with asending node of the wireless local area network,the apparatus furthercomprising a media access control device responsive to the carrierdetect signal by disabling the associated sending node from transmittinga signal.
 4. The apparatus according to claim 3, wherein the edgedetecting circuit includes a limit amplifier generating a square wavepulse signal corresponding to the intermediate frequency signal, thesquare wave pulse signal having rising edges, andwherein the edgedetecting circuit detects the rising edges of the square wave pulsesignal.
 5. The apparatus according to claim 4, wherein the comparisoncircuit includesa storage circuit coupled to the first counter circuitand storing the first and second counts representing the respective timeperiods of the first and second cycles of a pair of consecutive cyclesof the intermediate frequency signal; a decoder circuit coupled to thestorage circuit and outputting a first signal when the initial count ofcycles is less than the first predetermined number; and an adder circuitcoupled to the storage circuit and outputting the difference signal whenthe difference between the first and second counts is less than thethird predetermined number.
 6. The apparatus according to claim 5,wherein the second counter circuit is responsive to the first signal byresetting the count of cycles of the intermediate frequency signal. 7.The apparatus according to claim 6, wherein the phase shift keyedmodulated signal represents a binary signal,wherein the square wavepulse signal generated by the limit amplifier includes falling edges,and wherein the edge detecting circuit detects consecutive falling edgesof the square wave pulse signal, two consecutive falling edgesrepresenting a time period of a cycle of the intermediate frequencysignal, the apparatus further comprising a third counter circuitresponsive to the edge detecting circuit by generating a plurality ofcounts, each count counted by the third counter circuit being a numberof cycles of the reference frequency signal occurring between twoconsecutive falling edges; and a data output circuit responsive to therespective counts of the first and third counter circuits by generatingan output signal that is a composite representation of the binarysignal.
 8. The apparatus according to claim 7, further comprising afrequency compensation circuit responsive to the second counter circuitby outputting a frequency compensation signal when the second countercircuit generates the carrier detect signal, the frequency compensationsignal being related to a difference between a time period of a cycle ofthe intermediate frequency signal and a time period of one cycle of thenominal center frequency.
 9. The apparatus according to claim 8, whereinthe first and third counter circuits are coupled to the frequencycompensation signal, andwherein the first and third counter circuitseach output a plurality of counts that are offset by the frequencycompensation signal.
 10. The apparatus according to claim 9, wherein thesecond predetermined number corresponds to about 50 ns, the thirdpredetermined number corresponds to about 36 ns, and the fourthpredetermined number corresponds to about 74 cycles of the intermediatefrequency signal.
 11. The apparatus according to claim 9, wherein afterthe carrier detect signal is generated, the comparison circuit comparesa third count of cycles of the reference frequency counted by the firstcounter circuit to the first predetermined number, the comparisoncircuit terminating the difference signal when a difference between thethird count and the first predetermined number equals or exceeds a fifthpredetermined number; andwherein the second counter circuit isresponsive to termination of the difference signal by counting cycles ofthe intermediate frequency signal and terminating the carrier detectsignal when a count of the intermediate frequency signal cycles equals asixth predetermined number.
 12. The apparatus according to claim 11,wherein the fifth predetermined number corresponds to about 55 ns, andthe sixth predetermined number corresponds to about 5 cycles of theintermediate frequency signal.
 13. The apparatus according to claim 11,wherein the media access control device is responsive to termination ofthe carrier detect signal by enabling the associated sending node fortransmitting a signal.
 14. A method of detecting a carrier signal of aphase shift keyed modulated signal, the method comprising the stepsof:generating an intermediate frequency signal from a received phaseshift keyed modulated signal, the intermediate frequency signal having anominal center frequency; determining a difference between a time periodof a first cycle of the intermediate frequency signal and a time periodof one cycle of the nominal center frequency; determining a firstdifference between cycle time periods of each cycle for each pair ofconsecutive cycles of the intermediate frequency signal for a firstpredetermined number of consecutive cycles of the intermediate frequencysignal when the determined difference between the time period of thefirst cycle of the intermediate frequency signal and the time period ofone cycle of the nominal center frequency is less than a predeterminedperiod of time, the consecutive cycles being subsequent to the firstcycle; and generating a carrier detect signal when the first differencebetween cycle time periods of each cycle for each pair of the firstpredetermined number of consecutive cycles of the intermediate frequencyis less than a first predetermined cycle time period difference.
 15. Themethod according to claim 14, further comprising the step of disablingtransmission of a signal when the carrier detect signal is generated.16. The method according to claim 14, wherein the step of generating anintermediate frequency signal includes the step of forming a square wavepulse signal from the received signal, the square wave pulse signalhaving rising and falling edges; andwherein the step of determining thedifference between the time period of the first cycle of theintermediate frequency signal and the time period of one cycle of thenominal center frequency includes the steps of:detecting first andsecond consecutive rising edges of the square wave pulse signal, thefirst and second consecutive rising edges representing the first cycleof the intermediate frequency signal; measuring a first number ofperiods of a first predetermined frequency signal occurring between thefirst and second rising edges, the first number representing the timeperiod of the first cycle; and comparing the first number with apredetermined number, the predetermined number representing the timeperiod of one cycle of the nominal center frequency.
 17. The methodaccording to claim 16, wherein the step of determining the firstdifference between cycle time periods of each cycle for each pair ofconsecutive cycles of the intermediate frequency signal includes thesteps of:detecting third and fourth consecutive rising edges of thesquare wave pulse signal, the third and fourth consecutive rising edgesrepresenting a first cycle of a pair of consecutive cycles of theintermediate frequency signal; measuring a second number of periods ofthe first predetermined frequency signal occurring between the third andfourth rising edges, the second number representing the time period ofthe first cycle of the pair of consecutive cycles; detecting a fifthrising edge of the square wave pulse signal, the fifth rising edge beingconsecutive to the fourth rising edge, the fourth and fifth consecutiverising edges representing a second cycle of the pair of consecutivecycles; measuring a third number of periods of the first predeterminedfrequency signal occurring between the fourth and fifth rising edges,the third number representing the time period of the second cycle of thepair of consecutive cycles; and determining a difference between thesecond number and the third number.
 18. The method according to claim17, wherein the first and second rising edges are the third and fourthrising edges, respectively, such that the first cycle of theintermediate frequency signal is the first cycle of the pair ofconsecutive cycles.
 19. The method according to claim 16, wherein thereceived signal represents a binary signal, the method furthercomprising the step of demodulating the received signal to generate anoutput signal that is a composite representation of the binary signalwhen the carrier detect signal is generated.
 20. The method according toclaim 19, wherein the step of demodulating the received signal includesthe steps of:measuring first time intervals between consecutive risingedges of the square wave pulse signal; measuring second time intervalsbetween consecutive falling edges of the square wave pulse signal; andgenerating the output signal based on results of the first and secondtime interval measurements.
 21. The method according to claim 20,further comprising the steps of:measuring a cycle time period of asecond cycle of the intermediate frequency signal when the cycle timeperiod difference for each pair of the first predetermined number ofconsecutive cycles is less than the first predetermined cycle timeperiod difference, the second cycle being subsequent to the firstpredetermined number of consecutive cycles; generating a frequencycompensation factor based on the measured second cycle time period; andcompensating the first and second time intervals measurements for cycletime period deviations of the intermediate frequency signal from thecycle time period of the nominal center frequency using the frequencycompensation factor.
 22. The method according to claim 21, wherein thefirst predetermined number of corresponds to 74 consecutive cycles, thepredetermined period of time is about 50 ns, and the first predeterminedcycle time period difference is about 36 ns.
 23. The method according toclaim 21, further comprising the steps of:determining a seconddifference between cycle time periods of each cycle for each pair ofconsecutive cycles of the intermediate frequency signal for a secondpredetermined number of consecutive cycles of the intermediate frequencysignal after the carrier detect signal is generated; and terminating thecarrier detect signal when the second difference between cycle timeperiods of each cycle for each pair of the second predetermined numberof consecutive cycles of the intermediate frequency is less than asecond predetermined cycle time period difference.
 24. The methodaccording to claim 23, wherein the second predetermined number ofconsecutive cycles is about 5, and the second predetermined cycle timeperiod difference is about 55 ns.
 25. A wireless local area networkcomprising:a first node having a transmitting device transmitting aphase shift keyed modulated signal; and a second node having atransmitting device and a receiving device, the receiving devicereceiving the signal, the receiving device including,an intermediatefrequency generator generating an intermediate frequency signalcorresponding to the signal; a carrier detection circuit coupled to theintermediate frequency generator and measuring a time period of a cycleof the intermediate frequency signal and generating a first detectionsignal when a difference between the measured time period and a nominaltime period of the intermediate frequency signal is less than a firstpredetermined difference; a cycle-to-cycle difference circuit measuringa difference in time periods of two consecutive cycles of theintermediate frequency signal and generating a valid difference signalwhen the difference is less than a second predetermined difference; anda cycle difference counter circuit responsive to the first detectionsignal and the valid difference signal by counting cycles of theintermediate frequency signal and generating a carrier detect signalwhen a count of the intermediate frequency signal cycles equals a firstpredetermined number.
 26. The wireless network according to claim 25,wherein the receiving device further comprises a media access controldevice responsive to the carrier detect signal by disabling thetransmitting device of the second node from transmitting a signal. 27.The wireless network according to claim 26, wherein the carrierdetection circuit includes a memory circuit storing measured timeperiods of two consecutive cycles of the intermediate frequency signal,and a decoder circuit generating the first detection signal when thedifference between one of the stored measured time periods and thenominal time period of the intermediate frequency signal is less thanthe first predetermined difference; andwherein the cycle-to-cycledifference circuit includes an adder circuit coupled to the memorycircuit and outputting the valid difference signal when the differencebetween the two stored measured time periods is less than the secondpredetermined difference.
 28. The wireless network according to claim27, wherein the decoder circuit terminating the first detection signalwhen the difference between the one of the stored measured time periodsand the nominal time period of the intermediate frequency signal equalsor exceeds the first predetermined difference, andwherein the cycledifference counter circuit is responsive to termination of the firstdetection signal by setting the count of the cycles of the intermediatefrequency signal.
 29. The wireless network according to claim 28,wherein the phase shift keyed modulated signal represents a binarysignal, andwherein the receiving device further includes a demodulatorcircuit generating a composite output signal corresponding to the binarysignal when the carrier detect signal is generated.
 30. The wirelessnetwork according to claim 29, wherein the receiving device furtherincludes a frequency compensation circuit responsive to the carrierdetect signal by generating a frequency compensation signal, thefrequency compensation signal being related to a difference between atime period of a cycle of the intermediate frequency signal and a timeperiod of one cycle of the nominal center frequency.
 31. The wirelessaccording to claim 30, wherein the memory circuit is coupled to thefrequency compensation signal, and the measured time periods of the twoconsecutive cycles of the intermediate frequency signal are compensatedby the frequency compensation signal.
 32. The wireless network accordingto claim 31, wherein the first predetermined number corresponds to about50 ns, the second predetermined number corresponds to about 36 ns, andthe first predetermined number corresponds to about 74 cycles of theintermediate frequency signal.
 33. The wireless network according toclaim 31, wherein after the carrier detect signal is generated, thecycle difference counter circuit measures a difference between a timeperiod of a cycle of the intermediate frequency signal and the nominaltime period of the intermediate frequency signal, and generates a validdifference signal when the difference is less than a third predetermineddifference and terminates the valid difference signal when thedifference equals or exceeds the third predetermined difference;andwherein the cycle difference counter circuit is responsive totermination of the valid difference signal by counting cycles of theintermediate frequency signal and terminating the carrier detect signalwhen a count of the intermediate frequency signal cycles equals a secondpredetermined number.
 34. The wireless network according to claim 33,wherein the third predetermined difference corresponds to about 55 ns,and the second predetermined number corresponds to about 5 cycles of theintermediate frequency signal.
 35. The wireless network according toclaim 33, wherein the media access control device is responsive totermination of the carrier detect signal by enabling the transmittingdevice of the second node for transmitting a signal.